? semiconductor components industries, llc, 2000 march, 2000 rev. 4 1 publication order number: mc10h644/d
the mc10h/100h644 generates the necessary clocks for the 68030, 68040 and similar microprocessors. the device is functionally equivalent to the h640, but with fewer outputs in a smaller outline 20lead plcc package. it is guaranteed to meet the clock specifications required by the 68030 and 68040 in terms of parttopart skew, withinpart skew and also duty cycle skew. the user has a choice of using either ttl or pecl (ecl referenced to +5.0v) for the input clock. ttl clocks are typically used in present mpu systems. however, as clock speeds increase to 50mhz and beyond, the inherent superiority of ecl (particularly differential ecl) as a means of clock signal distribution becomes increasingly evident. the h644 also uses differential ecl internally to achieve its superior skew characteristic. the h644 includes dividebytwo and dividebyfour stages, both to achieve the necessary duty cycle and skew to generate mpu clocks as required. a typical 50mhz processor application would use an input clock running at 100mhz, thus obtaining output clocks at 50mhz and 25mhz (see logic symbol). the 10h version is compatible with mecl 10h ? ecl logic levels, while the 100h version is compatible with 100k levels (referenced to +5.0v). ? generates clocks for 68030/040 ? meets 68030/040 skew requirements ? ttl or pecl input clock ? extra ttl and ecl power/ground pins ? within device skew on similar paths is 0.5 ns ? asynchronous reset ? single +5.0v supply function reset (r): low on reset forces all q outputs low and all q outputs high. synchronized outputs: the device is designed to have the pos edges of the 2 and 4 outputs synchronized. select (sel): low selects the pecl input source (de/de ). high selects the ttl input source (dt). the h644 also contains circuitry to force a stable state of the pecl input differential pair, should both sides be left open. in this case, the de side of the input is pulled low, and de goes high. http://onsemi.com device package shipping ordering information mc10h644fn plcc20 37 units/rail marking diagram a = assembly location wl = wafer lot yy = year ww = work week plcc20 fn suffix case 775 10h644 awlyyww 1 mc100h644fn plcc20 37 units/rail
mc10h644, mc100h644 http://onsemi.com 2 gt q3 gt q2 gt q4 vt q5 gt r ve de v bb de ge q1 vt q0 sel dt 19 18 13 17 16 15 14 12 11 10 9 45678 20 1 2 3 pinout: 20lead plcc (top view) 4 vbb ttl outputs q5 q4 q3 q2 q1 q0 2 2:1 mux de (ecl) de (ecl) dt (ttl) sel (ttl) r (ttl) logic diagram pin names pin function gt vt ve ge de, de v bb dt qn, qn sel r ttl ground (0v) ttl v cc (+5.0v) ecl v cc (+5.0v) ecl ground (0v) ecl signal input (positive ecl) v bb reference output ttl signal input signal outputs (ttl) input select (ttl) reset (ttl)
mc10h644, mc100h644 http://onsemi.com 3 ac characteristics (vt = ve = 5.0 v 5%) 0 c 25 c 85 c symbol characteristic min max min max min max unit condition t plh propagation delay ecl d to output all outputs 5.8 6.8 5.7 6.7 6.1 7.1 ns cl = 50pf t plh propagation delay ttl d to output 5.7 6.7 5.7 6.7 6.0 7.0 ns cl = 50pf t skwd * withindevice skew q0, 1, 4, 5 0.5 0.5 0.5 ns cl = 50pf t skwd * withindevice skew q2 , q3 0.5 0.5 0.5 ns cl = 50pf t skwd * withindevice skew all outputs 1.5 1.5 1.5 ns cl = 50pf t skpp * parttopart skew q0, 1, 4, 5 1.0 1.0 1.0 ns cl = 50pf t pd propagation delay r to output all outputs 4.3 7.3 4.3 7.3 4.5 7.5 ns cl = 50pf t r t f output rise/fall time 0.8v 2.0v all outputs 1.6 1.6 1.6 ns cl = 50pf f max maximum input frequency 135 135 135 mhz cl = 50pf tw minimum pulse width reset 1.5 1.5 1.5 ns t rr reset recovery time 1.25 1.25 1.25 ns t pw pulse width out high or low @ f in = 100 mhz and cl = 50 pf q0, 1 9.5 10.5 9.5 10.5 9.5 10.5 ns cl = 50pf relative 1.5v ts setup time sel to de, dt 2.0 2.0 2.0 ns th hold time sel to de, dt 2.0 2.0 2.0 ns * skews are specified for identical edges
mc10h644, mc100h644 http://onsemi.com 4 dc characteristics (vt = ve = 5.0 v 5%) 0 c 25 c 85 c symbol characteristic min max min max min max unit condition i ee power supply current ecl 65 65 65 ma ve pin i cc ttl 85 85 85 ma total all v t pins ttl dc characteristics (vt = ve = 5.0 v 5%) 0 c 25 c 85 c symbol characteristic min max min max min max unit condition v ih v il input high voltage input low voltage 2.0 0.8 2.0 0.8 2.0 0.8 v i ih input high current 20 100 20 100 20 100 m a v in = 2.7 v v in = 7.0 v i il input low current 0.6 0.6 0.6 ma v in = 0.5 v v oh output high voltage 2.5 2.0 2.5 2.0 2.5 2.0 v i oh = 3.0 ma i oh = 24 ma v ol output low voltage 0.5 0.5 0.5 v i ol = 24 ma v ik input clamp voltage 1.2 1.2 1.2 v i in = 18 ma i os output short circuit current 100 225 100 225 100 225 ma v out = 0 v 10h pecl dc characteristics (vt = ve = 5.0 v 5%) 0 c 25 c 85 c symbol characteristic min max min max min max unit condition i inh i inl input high current input low current 0.5 225 0.5 175 0.5 175 m a v ih * v il * input high voltage input low voltage 3.83 3.05 4.16 3.52 3.87 3.05 4.19 3.52 3.94 3.05 4.28 3.55 v ve = 5.0 v v bb * output reference voltage 3.62 3.73 3.65 3.75 3.69 3.81 v ve = 5.0 v 100h pecl dc characteristics (vt = ve = 5.0 v 5%) 0 c 25 c 85 c symbol characteristic min max min max min max unit condition i inh i inl input high current input low current 0.5 225 0.5 175 0.5 175 m a v ih * v il * input high voltage input low voltage 3.835 3.19 4.12 3.525 3.835 3.19 4.12 3.525 3.835 3.19 4.12 3.525 v ve = 5.0 v v bb * output reference voltage 3.62 3.74 3.62 3.74 3.62 3.74 v ve = 5.0 v * note: pecl levels are referenced to v cc and will vary 1:1 with the power supply. the values shown are for v cc = 5.0 v. only corresponds to ecl clock inputs.
mc10h644, mc100h644 http://onsemi.com 5 package dimensions plcc20 fn suffix plastic plcc package case 77502 issue c notes: 1. datums l, m, and n determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum t, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). m n l y brk w v d d s lm m 0.007 (0.180) n s t s lm m 0.007 (0.180) n s t s lm s 0.010 (0.250) n s t x g1 b u z view dd 20 1 s lm m 0.007 (0.180) n s t s lm m 0.007 (0.180) n s t s lm s 0.010 (0.250) n s t c g view s e j r z a 0.004 (0.100) t seating plane s lm m 0.007 (0.180) n s t s lm m 0.007 (0.180) n s t h view s k k1 f g1 dim min max min max millimeters inches a 0.385 0.395 9.78 10.03 b 0.385 0.395 9.78 10.03 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 0.51 k 0.025 0.64 r 0.350 0.356 8.89 9.04 u 0.350 0.356 8.89 9.04 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y 0.020 0.50 z 2 10 2 10 g1 0.310 0.330 7.88 8.38 k1 0.040 1.02
mc10h644, mc100h644 http://onsemi.com 6 notes
mc10h644, mc100h644 http://onsemi.com 7 notes
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